3.3V 256K x 18 Synchronous PipeLined Burst SRAM w/2.5V IDT71V2578S-133PFI [x24]

The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges.

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